CPUID
In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU IDentification) allowing software to discover details of the processor. It was introduced by Intel in 1993 with the launch of the Pentium and SL-enhanced 486 processors. A program can use the CPUID to determine processor type and whether features such as MMX/SSE are implemented.
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CPU flag (x86)CpuidIndirect Branch ControlIndirect Branch Control ExtensionIndirect Branch Prediction BarrierIndirect Branch Restricted SpeculationIndirect branch controlIndirect branch control extensionIndirect branch prediction barrierIndirect branch restricted speculationSTIBPSingle Thread Indirect Branch PredictorSingle thread indirect branch predictorSpeculative Store Bypass DisableSpeculative store bypass disableSsbd
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AMD 10hAMD K6AMD K6-2AMD K8Alternate Instruction SetBit manipulation instruction setBranch predictorBranch target predictorCLMUL instruction setCPU-ZCPU flag (x86)Clarkdale (microprocessor)CpuidCyrix 6x86F16CFLAGS registerFMA instruction setFat binaryGeode (processor)GulftownHans Peter AnvinIBCIBPBIBRSIndirect Branch ControlIndirect Branch Control ExtensionIndirect Branch Prediction BarrierIndirect Branch Restricted SpeculationIndirect branchIndirect branch controlIndirect branch control extensionIndirect branch prediction barrierIndirect branch restricted speculationIntel CoreIntel Core (microarchitecture)Intel MicrocodeList of AMD CPU microarchitecturesLong modeMath Kernel LibraryMemory management unit
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CPUID
In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU IDentification) allowing software to discover details of the processor. It was introduced by Intel in 1993 with the launch of the Pentium and SL-enhanced 486 processors. A program can use the CPUID to determine processor type and whether features such as MMX/SSE are implemented.
has abstract
CPUID (CPU Identification) — а ...... UMC U5S. Код операції: 0F A2.
@uk
CPUID (CPU Identification) — а ...... UMC U5S. Код операции: 0F A2.
@ru
CPUID je symbolické pojmenován ...... it, zda ji procesor podporuje.
@cs
CPUID opcode는 x86 아키텍처를 위한 프로세 ...... 러일으킬 수 있는 비밀스러운 기계어를 기록하여야 했다.
@ko
CPUIDは、x86の機械語命令の一つ（およびそのアセンブリ ...... による変化前と変化後の、どちらの値がプッシュされるか、等）。
@ja
CPUID是一个面向x86架构的，它的名称衍生自CPU识别， ...... EAX寄存器中，某些情况下ECX寄存器用于指定要返回的信息。
@zh
Dans l'architecture x86, l'ins ...... ue et le modèle du processeur.
@fr
Die CPUID-Kennung ist seit den ...... te Adressierungsmöglichkeiten.
@de
In informatica, CPUID è un ass ...... ti distintivi delle varie CPU.
@it
In the x86 architecture, the C ...... ch as MMX/SSE are implemented.
@en
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1,025,031,461
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CPUID (CPU Identification) — а ...... UMC U5S. Код операції: 0F A2.
@uk
CPUID (CPU Identification) — а ...... UMC U5S. Код операции: 0F A2.
@ru
CPUID je symbolické pojmenován ...... it, zda ji procesor podporuje.
@cs
CPUID opcode는 x86 아키텍처를 위한 프로세 ...... 러일으킬 수 있는 비밀스러운 기계어를 기록하여야 했다.
@ko
CPUIDは、x86の機械語命令の一つ（およびそのアセンブリ ...... による変化前と変化後の、どちらの値がプッシュされるか、等）。
@ja
CPUID是一个面向x86架构的，它的名称衍生自CPU识别， ...... EAX寄存器中，某些情况下ECX寄存器用于指定要返回的信息。
@zh
Dans l'architecture x86, l'ins ...... que MMX/SSE sont disponibles.
@fr
Die CPUID-Kennung ist seit den ...... te Adressierungsmöglichkeiten.
@de
In informatica, CPUID è un ass ...... set di istruzioni MMX o SSE).
@it
In the x86 architecture, the C ...... ch as MMX/SSE are implemented.
@en
label
CPUID
@cs
CPUID
@de
CPUID
@en
CPUID
@fr
CPUID
@it
CPUID
@ja
CPUID
@ko
CPUID
@ru
CPUID
@uk
CPUID
@zh