Standard cell
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology — the general class to which standard cells belong — makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates)
product
Wikipage disambiguates
Wikipage redirect
Application-specific integrated circuitArm Ltd.Cell-based ICCell (EDA)Circuit underutilizationComputer engineering compendiumDolphin IntegrationFPGA prototypingFull customGajski-Kuhn chartGate arrayGate equivalentGlitch removalGraph bandwidthHardware description languageIEEE Robert N. Noyce MedalIntegrated circuit designIntegrated circuit layoutLibrary (disambiguation)Library (electronics)List of International Electrotechnical Commission standardsList of file formatsMOSAIDMacrocell arrayNOR logicNanGatePokerTrackerProcessor designRandom logicSemiconductor intellectual property coreSignoff (electronic design automation)StandardStandard CellSystem on a chipTechnology aware designTypes of physical unclonable function
Link from a Wikipage to another Wikipage
primaryTopic
Standard cell
In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology — the general class to which standard cells belong — makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates)
has abstract
In semiconductor design, stand ...... ystem-on-a-chip (SoC) devices.
@en
Проектирование на основе станд ...... стигающем десятков миллиардов.
@ru
在半导体设计中,标准单元设计方法是指一种特殊應用積體電路设计中使用数字逻辑的方法。 一个标准单元是指一系列由晶体管和连线结构组成的具有布尔逻辑功能或者触发功能的数字单元。
@zh
Link from a Wikipage to an external page
Wikipage page ID
page length (characters) of wiki page
Wikipage revision ID
980,319,301
Link from a Wikipage to another Wikipage
wikiPageUsesTemplate
hypernym
type
comment
In semiconductor design, stand ...... Cs (of several thousand gates)
@en
Проектирование на основе станд ...... стигающем десятков миллиардов.
@ru
在半导体设计中,标准单元设计方法是指一种特殊應用積體電路设计中使用数字逻辑的方法。 一个标准单元是指一系列由晶体管和连线结构组成的具有布尔逻辑功能或者触发功能的数字单元。
@zh
label
Standard cell
@en
Standardzelle
@de
Проектирование на основе стандартных ячеек
@ru
标准单元
@zh
표준셀
@ko