ESi-RISC
eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.
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ESi-RISC
eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.
has abstract
eSi-RISC is a configurable CPU ...... ing into both ASICs and FPGAs.
@en
eSi-RISCは変更可能なCPUアーキテクチャで、EnSi ...... コアであり、ASICとFPGAのいずれにも使うことができる。
@ja
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@en
design
RISC
@en
designer
eSi-RISC
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encoding
Intermixed 16 and 32-bit
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endianness
Big or little
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extensions
User-defined instructions
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introduced
name
eSi-RISC
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registers
type
Register-Register
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wikiPageUsesTemplate
subject
hypernym
type
comment
eSi-RISC is a configurable CPU ...... ing into both ASICs and FPGAs.
@en
eSi-RISCは変更可能なCPUアーキテクチャで、EnSi ...... コアであり、ASICとFPGAのいずれにも使うことができる。
@ja
label
ESi-RISC
@en
ESi-RISC
@ja