Second Level Address Translation
Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables. AMD has supported SLAT through the Rapid Virtualization Indexing (RVI) technology since the introduction of its third-generation Opteron processors (code name Barcelona). Intel's implementation of SLAT, known as Extended Page Table (EPT), was introduced in the Nehalem microarchitecture found in certain Core i7, Core i5, and Core i3 processors.
AMD-V Nested PagingAMD 10hEPTExtended Page TableHardware-assisted virtualizationHyper-VIntel eptLGA 775List of AMD CPU microarchitecturesList of IOMMU-supporting hardwareList of Intel Atom microprocessorsList of Intel Broadwell-based Xeon microprocessorsList of Intel Celeron microprocessorsList of Intel Core i3 processorsList of Intel Haswell-based Xeon microprocessorsList of Intel Ivy Bridge-based Xeon microprocessorsList of Intel Nehalem-based Xeon microprocessorsList of Intel Pentium processorsList of Intel Sandy Bridge-based Xeon microprocessorsList of Intel Skylake-based Xeon microprocessorsMicrosoft Visual Studio ExpressNPTNehalem (microarchitecture)Nested Page TableNested Page TablesNested pagingOpteronPage tableRVIRapid Virtualization IndexingRemoteFXSLATSLAT-enabled processorsSecond-level address translationSlatVirtualBoxVirtual 8086 modeWindows 10Windows 8Windows Server 2012
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Second Level Address Translation
Second Level Address Translation (SLAT), also known as nested paging, is a hardware-assisted virtualization technology which makes it possible to avoid the overhead associated with software-managed shadow page tables. AMD has supported SLAT through the Rapid Virtualization Indexing (RVI) technology since the introduction of its third-generation Opteron processors (code name Barcelona). Intel's implementation of SLAT, known as Extended Page Table (EPT), was introduced in the Nehalem microarchitecture found in certain Core i7, Core i5, and Core i3 processors.
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La paginación anidada o nested ...... Intelequivalente es la EPT, .
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SLAT (англ. Second Level Addre ...... и 64-разрядной) архитектурах.
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Second Level Address Translati ...... bit and 64-bit) architectures.
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Second Level Address Translati ...... nd Core-i3-Klasse unterstützt.
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第二層位址轉譯（英語：Second Level Addres ...... eSLATStatusCheck檢測處理器是否支援SLAT。
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La paginación anidada o nested ...... Intelequivalente es la EPT, .
@es
SLAT (англ. Second Level Addre ...... и 64-разрядной) архитектурах.
@ru
Second Level Address Translati ...... re i5, and Core i3 processors.
@en
Second Level Address Translati ...... nd Core-i3-Klasse unterstützt.
@de
第二層位址轉譯（英語：Second Level Addres ...... eSLATStatusCheck檢測處理器是否支援SLAT。
@zh
label
Paginación anidada
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SLAT
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Second Level Address Translation
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Second Level Address Translation
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第二層位址轉譯
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