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Zener Zap Anti-Fuse Trim in VLSI CircuitsCORDIC Architectures: A SurveyA Generalized Tunneling Formula for Quantum Device ModelingResolution of Resonances in a General Purpose Quantum Device Simulator (NEMO)Analytical Engines are Unnecessary in Top-down Partitioning-based PlacementA Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector ApproachLow-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video EncoderA Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter CoefficientsHomogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal ProcessingA Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror ActuationAn Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product CodesA Programmable Hardware Cellular Automaton: Example of Data Flow TransformationSelected Papers from the International Mixed Signals Testing and GHz/Gbps Test WorkshopAntirandom Testing: A Distance-Based ApproachDesign and Characterization of the Next Generation Nanowire AmplifiersDelay Efficient 32-Bit Carry-Skip AdderA Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nmA Pull-in Based Test Mechanism for Device Diagnostic and Process CharacterizationMEMS Switches and SiGe Logic for Multi-GHz Loopback TestingUsing Signal Envelope Detection for Online and Offline RF MEMS Switch TestingDesign and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless ReceiverA Programmable Max-Log-MAP Turbo Decoder ImplementationEnabling VLSI Processing Blocks for MIMO-OFDM CommunicationsBuilt-in Test Enabled Diagnosis and Tuning of RF Transmitter SystemsA Dependable Microelectronic Peptide Synthesizer Using Electrode DataADC Production Test Technique Using Low-Resolution Arbitrary Waveform GeneratorVLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting SchemeA Phase-Locked Loop with 30% Jitter Reduction Using Separate RegulatorsFine Control of Local Whitespace in PlacementChoice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing TestAn FFT Core for DVB-T/DVB-H ReceiversInternational Conference on Electronics, Circuits, and SystemsSimple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral ApproachPower Considerations in Banked CAMs: A Leakage Reduction ApproachA Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated SequencesWave Pipelining Using Self Reset LogicHigh-Performance Timing-Driven Rank FilterFigure-of-Merit-Based Area-Constrained Design of Differential AmplifiersFully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion EstimationA Time-Consistent Video Segmentation Algorithm Designed for Real-Time Implementation
P1433
Q21342998-C19FC343-042B-4496-8E8E-12B24A5EF6BAQ56442733-0E978B86-4EA9-43DE-8504-AD1CE52BB45AQ57370086-2134618D-E36C-4294-9937-2DA83C040229Q57370123-67EBB9B2-1385-47F6-A290-31524D6340F1Q57397374-5157C995-31F2-4875-AA99-B7FC8C402D19Q57743984-8DC0BAAB-E9E1-40DE-9494-A6045BCE11CFQ57760109-AD46C420-D40F-4D7B-BA98-065198352EE2Q58208895-7647FE45-A11E-4784-97D8-B60369470644Q58632204-187087D4-DD39-4325-BEC5-682A3FECACF1Q58632407-EBAB4ECA-D7ED-4204-BF37-AB5FFE5CB863Q58646426-304E619C-15FC-4EF3-B906-4ACC8E6C48CBQ58646427-8A9428B3-D57E-457D-9025-EC86B11038F5Q58646430-FE15808A-4054-41DE-9DBF-D30C6BCC77ABQ58646431-6F6B421B-AB6D-435C-A71D-6C103845E7CCQ58646433-E82FEF34-E0DE-4521-9B60-8BE4BA096E33Q58646434-F1969566-FFF3-4883-83D8-EFDDBA68EE05Q58646436-942A76DE-5657-43AF-96FC-C587E0D2BBF4Q58646440-925681C9-2326-4575-8029-56D486B326A8Q58646442-F505EBC3-AF86-4DE2-8A8B-63CAAEF141F0Q58646444-D3F2580D-3F8A-44A5-8C1E-58ABEB7280DBQ58646446-0B32E6DE-20F4-4036-AFBB-E8D4CE0AFCFEQ58646449-9D834181-CFF4-4988-B923-5CE94E85AA8AQ58646452-706E814D-6138-4C04-BD68-161F89C3A05DQ58646454-871C72F9-77E0-4759-AE0D-6268A944DB94Q58646456-46F448CB-3D4E-4BE3-88FC-B8C10AD37B10Q58646459-16D03F00-40CF-4A95-9023-E045D17CB223Q58646461-6198B88D-2D52-4134-93F5-01A321C544BDQ58646463-22FB59A8-5D21-448F-8627-A55352E4B4CEQ58646466-BE67D328-9C30-45AF-917B-4760FA4DB3B1Q58646468-FAC55B13-DD50-4768-A23C-96039E01895EQ58646470-87CB7832-139C-4214-9F2C-84D56C8A07C4Q58646472-FBA73AC3-E6E3-48D8-AED7-144544443E17Q58646473-0ED8BC25-B034-49FC-AA3C-68479AFCE567Q58646477-F9A1D32E-DA64-4B40-8A3E-176E089F2AEDQ58646480-8A38AA86-913D-4E6D-AE7C-CA8A6194BC96Q58646484-6C903A6E-D9E4-426E-A2AF-5F1326219024Q58646486-FCDFA22C-0666-4189-B7A5-0126E21F9957Q58646487-F6B0CF87-9818-4042-ABC0-6A4899CF6612Q58646491-348CBD39-120B-4548-9989-F56B14878B49Q58646494-4CF893BE-9CD4-4641-A4F9-67ABC7BEF456
P1433
description
journal
@en
revista científica
@es
rivista scientifica
@it
wetenschappelijk tijdschrift van Hindawi Publishing Corporation
@nl
wissenschaftliche Fachzeitschrift
@de
مجلة
@ar
name
V L S I Design
@da
VLSI Design
@ast
VLSI Design
@en
VLSI Design
@es
VLSI Design
@fi
VLSI Design
@fr
VLSI Design
@it
VLSI Design
@nb
VLSI Design
@nl
VLSI Design
@nn
type
label
V L S I Design
@da
VLSI Design
@ast
VLSI Design
@en
VLSI Design
@es
VLSI Design
@fi
VLSI Design
@fr
VLSI Design
@it
VLSI Design
@nb
VLSI Design
@nl
VLSI Design
@nn
prefLabel
V L S I Design
@da
VLSI Design
@ast
VLSI Design
@en
VLSI Design
@es
VLSI Design
@fi
VLSI Design
@fr
VLSI Design
@it
VLSI Design
@nb
VLSI Design
@nl
VLSI Design
@nn
P3181
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VLSI Design
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