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Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as BackendA Multicore Processor for Time-Critical ApplicationsSelected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time SystemsA resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chipCan real-time systems benefit from dynamic partial reconfiguration?High-level synthesis for reduction of WCET in real-time systemsTiming Organization of a Real-Time Multicore ProcessorAn area-efficient TDM NoC supporting reconfiguration for mode changesArgo: A Real-Time Network-on-Chip Architecture With an Efficient GALS ImplementationAvionics Applications on a Time-Predictable Chip-MultiprocessorReconfiguration in FPGA-based multi-core platforms for hard real-time applicationsState-based Communication on Time-predictable Multicore ProcessorsInterfacing hardware accelerators to a time-division multiplexing network-on-chipT-CREST: Time-predictable multi-core architecture for embedded systemsThe Argo NOC: Combining TDM and GALSA Metaheuristic Scheduler for Time Division Multiplexed Networks-on-ChipArgo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous RoutersOpen core protocol (OCP) clock domain crossing interfacesSynthesis and layout of an asynchronous network-on-chip using Standard EDA toolsA 65-nm CMOS area optimized de-synchronization flow for sub-V T designsAn Area-efficient Network Interface for a TDM-based Network-on-ChipRouter Designs for an Asynchronous Time-Division-Multiplexed Network-on-ChipA Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time SystemsDesign of Networks-on-Chip for Real-Time Multi-processor Systems-on-ChipIR-drop reduction in sub-V T circuits by de-synchronizationAnalytical derivation of traffic patterns in cache-coherent shared-memory systemsEnergy-minimum sub-threshold self-timed circuits using current-sensing completion detectionThe ReNoC Reconfigurable Network-on-ChipMinimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case StudyA Behavioral Synthesis Frontend to the Haste/TiDE Design FlowAnalytical derivation of traffic patterns in shared memory architectures from Task GraphsCurrent trends in high-level synthesis of asynchronous circuitsA Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution MethodAsynchronous design of networks-on-chipCustom topology generation for network-on-chipHardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time ProtocolUsing dynamic partial reconfiguration of FPGAs in real-Time systems
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description
professor ved DTU
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researcher ORCID ID = 0000-0002-0961-9438
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wetenschapper
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Jens Sparso
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Jens Sparso
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Jens Sparsø
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0000-0002-0961-9438
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2000-01-01T00:00:00Z