Online Test of Control Flow Errors: A New Debug Interface-Based ApproachUsing Benchmarks for Radiation Testing of Microprocessors and FPGAsAn error-detection and self-repairing method for dynamically and partially reconfigurable systemsOn the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW ProcessorsA New Fault Injection Approach for Testing Network-on-ChipsE-Learning at Politecnico di TorinoExperiences in the use of evolutionary techniques for testing digital circuitsQ57987027Test of Reconfigurable Modules in Scan NetworksScan-Chain Intra-Cell Aware TestingA Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity TransistorsA High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression AlgorithmsA suite of IEEE 1687 benchmark networksAn Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable SystemsBASTION: Board and SoC test instrumentation for ageing and no failure foundNew Techniques to Reduce the Execution Time of Functional Test ProgramsTowards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level EffectsA Flexible Framework for the Automatic Generation of SBST ProgramsEffective generation and evaluation of diagnostic SBST programsHybrid soft error mitigation techniques for COTS processor-based systemsIdentification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale CircuitsRejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler ProgramsTest Time Minimization in Reconfigurable Scan NetworksIn-field test of safety-critical systems: is functional test a feasible solution?On the Functional Test of Branch Prediction UnitsPartition-Based Faults Diagnosis of a VLIW ProcessorPermanent fault detection and diagnosis in the lightweight dual modular redundancy architectureSW-based transparent in-field memory testingAn effective approach to automatic functional processor test generation for small-delay faultsHigh Quality System Level Test and DiagnosisMIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-TestSelected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3–5, 2013Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players?An Efficient Method for the Test of Embedded Memory Cores during the Operational PhaseOn the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW ProcessorsOn the on-line functional test of the Reorder Buffer memory in superscalar processorsOn the Functional Test of Branch Prediction Units Based on the Branch History Table ArchitectureA Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and TestFunctional Verification of DMA ControllersImplementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor
P50
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P50
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hulumtues
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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Matteo Sonza Reorda
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P31
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2000-01-01T00:00:00Z