Multilevel hypergraph partitioning: applications in VLSI domain
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P2860
Q31045538-3F244322-E904-4DEE-ACDE-876748A13DA8Q33571711-6713F1DC-891C-4E42-861B-CB9543F56CA6Q35961181-B51ABBBF-31D5-44FA-AD95-5CC6CA6E4D12Q36763750-3D56201D-3674-40B2-9DA0-D826DEE6BA96Q57820146-1F72B744-6B95-48CF-B78E-C485ADD085CFQ58651888-4AB56B99-AF2C-46B0-9DF5-AE4F988F8B1EQ58915214-CE57A9D4-F5DE-4C31-8D68-29FBC9181B84
P2860
Multilevel hypergraph partitioning: applications in VLSI domain
description
wetenschappelijk artikel
@nl
наукова стаття, опублікована в березні 1999
@uk
name
Multilevel hypergraph partitioning: applications in VLSI domain
@en
Multilevel hypergraph partitioning: applications in VLSI domain
@nl
type
label
Multilevel hypergraph partitioning: applications in VLSI domain
@en
Multilevel hypergraph partitioning: applications in VLSI domain
@nl
prefLabel
Multilevel hypergraph partitioning: applications in VLSI domain
@en
Multilevel hypergraph partitioning: applications in VLSI domain
@nl
P2093
P356
P1476
Multilevel hypergraph partitioning: applications in VLSI domain
@en
P2093
G. Karypis
R. Aggarwal
S. Shekhar
P356
10.1109/92.748202
P577
1999-03-01T00:00:00Z