A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network
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A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network
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wetenschappelijk artikel
@nl
наукова стаття, опублікована в січні 2017
@uk
name
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@en
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@nl
type
label
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@en
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@nl
prefLabel
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@en
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@nl
P2093
P1476
A 5-Gb/s Digital Clock and Dat ...... ity Utilizing Coupling Network
@en
P2093
Lee-Sup Kim
Yong-Hun Kim
P304
P356
10.1109/TVLSI.2016.2566927
P577
2017-01-01T00:00:00Z