A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
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CNTFET-based design of multi-bit adder circuitsAn Energy Efficient Logic Approach to Implement CMOS Full AdderSimple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic CircuitsA High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder CellCNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder CircuitsDesign and analysis of a high-performance CNFET-based Full AdderA NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELLNovel direct designs for 3-input XOR function for low-power and high-speed applicationsPerformance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
P2860
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P2860
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
description
article
@en
wetenschappelijk artikel
@nl
наукова стаття, опублікована в червні 2005
@uk
name
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@en
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@nl
type
label
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@en
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@nl
prefLabel
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@en
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@nl
P2093
P1476
A review of 0.18-/spl mu/m ful ...... structured arithmetic circuits
@en
P2093
Chip-Hong Chang
Jiangmin Gu
Mingyan Zhang
P304
P356
10.1109/TVLSI.2005.848806
P577
2005-06-01T00:00:00Z