Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
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wetenschappelijk artikel
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наукова стаття, опублікована у вересні 2010
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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
@en
Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
@nl
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Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
@en
Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
@nl
P2093
P1476
Accelerating the Shuffled Frog Leaping algorithm by parallel implementations in FPGAs
@en
P2093
Carlos H. Llanos
Daniel M. Munoz
Leandro dos S. Coelho
P356
10.1109/BICTA.2010.5645270
P577
2010-09-01T00:00:00Z