about
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow RefractometryEquivalence checking using Gröbner basesLogic Synthesis for Majority Based In-Memory ComputingAn MIG-based compiler for programmable logic-in-memory architecturesAncilla-free synthesis of large reversible functions using binary decision diagramsApproximate BDD Optimization with Prioritized ε-Preferred Evolutionary AlgorithmApproximation-aware rewriting of AIGs for error tolerant applicationsAtomic distributions in crystal structures solved by Boolean satisfiability techniquesBDD minimization for approximate computingMulti-objective BDD optimization for RRAM based circuit designPrecise error determination of approximated components in sequential circuits with model checkingSimulation graphs for reverse engineeringSyReC: A hardware description language for the specification and synthesis of reversible circuitsTechnology Mapping of Reversible Circuits to Clifford+T Quantum CircuitsmetaSMT: focus on your application and not on solver integrationAutomated and quality-driven requirements engineeringAutomating the translation of assertions using natural language processing techniquesComplexity of reversible circuits and their quantum implementationsCoverage of OCL Operation Specifications and InvariantsEmbedding of Large Boolean Functions for Reversible LogicFormal Specification LevelMetaSMT: a unified interface to SMT-LIB2Multi-Objective BDD Optimization with Evolutionary AlgorithmsRequirement Phrasing Assistance Using Automatic Quality AssessmentReversible circuit rewriting with simulated annealingTechnology Mapping for Single Target Gate Based Circuits Using Boolean Functional DecompositionBehaviour Driven Development for Tests and VerificationFormal Specification LevelMapping NCV Circuits to Optimized Clifford+T CircuitsQuantum Circuit Optimization by Hadamard Gate ReductionRequirements Engineering for Cyber-Physical SystemsSelf-Verification as the Key Technology for Next Generation Electronic SystemsTrading off circuit lines and gate costs in the synthesis of reversible logicUpper bounds for reversible circuits based on Young subgroupsDebugging of Reversible Circuits Using pDDsExact Template Matching Using Boolean SatisfiabilityGrammar-based program generation based on model findingHardware-Software Co-Visualization: Developing systems in the holodeckImproving the mapping of reversible circuits to quantum circuits using multiple target linesLips: An IDE for model driven engineering based on natural language processing
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P50
description
onderzoeker
@nl
researcher ORCID ID = 0000-0002-0229-8766
@en
name
Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
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Mathias Soeken
@nl
P214
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P2456
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P496
0000-0002-0229-8766
P7859
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