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FPGA acceleration of rigid-molecule docking codes.Editorial: Selected Papers from NORCHIP '06Energy-minimum sub-threshold self-timed circuits using current-sensing completion detectionInversion schemes for sublithographic programmable logic arraysReliable computation with unreliable computersBrain-inspired computingAlgebraic approach to time borrowingInterconnection system for the SpiNNaker biologically inspired multi-computerModelling and simulation techniques for highly integrated, low-power wireless sensor networksReconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processorVery large scale integration architecture for integer wavelet transformSecure control protocol for universal serial bus mass storage devicesHardware implementation of a stereo co-processor in a medium-scale field programmable gate arrayDesign space extension for secure implementation of block ciphersProcessing while routing: a network-on-chip-based parallel systemField programmable gate array-based acceleration of shortest-path computationMethodology for adapting on-chip interconnect architecturesRouting of asynchronous Clos networksA universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuitsEditorial: Design of circuits and integrated systemsField programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio networkAdvanced verification by automatic property generationσ n LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chipImproving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structuresHybrid timing-address oriented load-store queue filtering for an x86 architectureEnergy reduction of the fetch mechanism through dynamic adaptationExploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debugMemory hierarchy for high-performance and energy-aware reconfigurable systemsOn the trade-off of mixing scientific applications on capacity high-performance computing systemsFour-level realisation of 3-qubit reversible functionsHybrid wire-surface wave interconnects for next-generation networks-on-chip
P1433
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P1433
description
journal
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revista científica
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rivista scientifica
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wetenschappelijk tijdschrift van Institution of Engineering and Technology
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wissenschaftliche Fachzeitschrift
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مجلة
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name
I E T Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
@es
IET Computers and Digital Techniques
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IET Computers and Digital Techniques
@fr
IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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type
label
I E T Computers and Digital Techniques
@da
IET Computers and Digital Techniques
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IET Computers and Digital Techniques
@en
IET Computers and Digital Techniques
@es
IET Computers and Digital Techniques
@fi
IET Computers and Digital Techniques
@fr
IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
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IET Computers and Digital Techniques
@nn
prefLabel
I E T Computers and Digital Techniques
@da
IET Computers and Digital Techniques
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IET Computers and Digital Techniques
@en
IET Computers and Digital Techniques
@es
IET Computers and Digital Techniques
@fi
IET Computers and Digital Techniques
@fr
IET Computers and Digital Techniques
@it
IET Computers and Digital Techniques
@nb
IET Computers and Digital Techniques
@nl
IET Computers and Digital Techniques
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P1055
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5800173367
P1250
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IET Computers and Digital Techniques
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