A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
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A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
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wetenschappelijk artikel
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наукова стаття, опублікована в серпні 2017
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name
A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
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A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@nl
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A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@en
A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@nl
prefLabel
A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@en
A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@nl
P2093
P1476
A hybrid memristor-CMOS multiplier design based on memristive universal logic gates
@en
P2093
Amirali Amirsoleimani
Majid Ahmadi
Mehri Teimoory
P356
10.1109/MWSCAS.2017.8053199
P50
P577
2017-08-01T00:00:00Z