An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
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article
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wetenschappelijk artikel
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наукова стаття, опублікована у 2008
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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
@en
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
@nl
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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
@en
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
@nl
P2093
P356
P1476
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
@en
P2093
Masahiro Iida
Masahiro Koga
Motoki Amagasaki
Ryoichi Yamaguchi
Toshinori Sueyoshi
P356
10.1155/2008/180216
P577
2008-01-01T00:00:00Z