Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.
about
A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.Integration of solid-state nanopores in a 0.5 μm CMOS foundry processLab-on-CMOS integration of microfluidics and electrochemical sensors.Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.
P2860
Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.
description
2011 nî lūn-bûn
@nan
2011年の論文
@ja
2011年論文
@yue
2011年論文
@zh-hant
2011年論文
@zh-hk
2011年論文
@zh-mo
2011年論文
@zh-tw
2011年论文
@wuu
2011年论文
@zh
2011年论文
@zh-cn
name
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@ast
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@en
type
label
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@ast
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@en
prefLabel
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@ast
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@en
P2093
P1476
Wafer Scale Integration of CMO ...... ions via Self-Aligned Masking.
@en
P2093
Ashfaque Uddin
Chin-Hsuan Chen
Kaveh Milaninia
Luke Theogarajan
P2860
P304
P356
10.1109/TCPMT.2011.2166395
P577
2011-12-01T00:00:00Z